Internship Program

Category

Full time

Duration

4 Weeks

Eligibility

3rd Year BE/Btech

Timings

9am - 5:30pm weekdays

Designing chips with today's power and area constraints is a challenging task. Good knowledge in basic electronics and a focused training with hands on experience in required areas are must to be a successful ASIC designer. Our course is structured to meet these requirements from the industry. This training course includes industry expert's talks and projects on industry standard projects, in addition to the interactive classroom sessions from working professionals.

Modules

Module-1: ADVANCED DIGITAL DESIGN

Review of Basic Digital Design, Complex combinational circuit designing, Design combinational circuit design using tristate devices, Review of sequential elements: latches and flip-flops, Finite state machine design: Sequence detectors, frequency dividers, Frequency synthesizers, synchronous and asynchronous counter design, Shift Registers and Memory design, FPGA Architectures.
Design Project: Dice game from specifications.

Module-2: STATIC TIMING ANALYSIS

Static timing analysis: introduction to timing analysis, comparison of STA over DTA, need for STA, Introduction to clock domain, single and multi-clock domain, clock domain crossing, Static timing analysis concepts. Fixing timing issues

Module-3: VERILOG HDL BASICS

Introduction to Verilog HDL, Syntax and Semantics of Verilog HDL, Data types and operators, Introduction to Design methodologies, Styles of modeling: Data flow, Structural, Gate level and Behavioral. Verification using simple test bench.

Module-4: HDL PROGRAMMING

Continuous assignment statements, Procedural assignment statement, control flow statements, Blocking and Non-blocking, race condition, Tasks and functions, Finite state machine coding styles.

Module-5: RTL DESIGN

Synthesis: Introduction to synthesis, Registers in Verilog, Unwanted latches, operator synthesis, RTL coding styles.

Module-6: VERIFICATION USING VERILOG HDL

Introduction to verification, classification of verification, Compiler Directives, system tasks, File management, Verilog event scheduling, Advanced test bench styles: Self checking test bench, Memory based test bench, test bench using file management, randomized test bench.

Module-7: STANDARD PROJECT

RTL Design and RTL Verification: Introduction, Specification Analysis, Architecture Preparation, Architecture Review, RTL coding, Project Review.

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