Inter Semester Program

Category

Full time

Duration

4 Weeks

Eligibility

BE/Btech/ME/MTech on going students.

Timings

9am - 5:30pm weekdays

Designing chips with today's power and area constraints is a challenging task. Good knowledge in basic electronics and a focused training with hands on experience in required areas are must to be a successful ASIC designer. Our course is structured to meet these requirements from the industry. This training course includes industry expert's talks and projects on industry standard projects, in addition to the interactive classroom sessions from working professionals.

Modules

Module-I :     INTRODUCTION

Introduction to the course,  Aim and Advantages of the course,  Introduction to VLSI,  Resent Trends in VLSI,  VLSI DESIGN FLOWS,  Full Custom and Semi Flows,  ASIC AND FPGA Design Flows,  A Simple Demo of the Design flow using EDA Tools,  CHIP Design Manufacturing Process,  Linux basics,  Lab Session on Linux Basics.

Module-II :     VERILOG BASICS

VERILOG HDL Concepts,  Design Methodologies,  Hierarchical modelling,  Verilog Basics,  Module,  Data types,  Operators,  Continuous assignment statements,  Procedural continuous assignment statements,  Control Flow statements,  Blocking and Non-Blocking statements,  Guide lines for Blocking,  Non-Blocking statements,  Looping statements,  Tasks and Functions,  Compiler directives,  System Tasks,   Assignments on above topics,  Lab session - Assignments include design and verifying RTL.

Module-III :     ADVANCED DIGITAL DESIGN CONCEPTS-COMBINATIONAL

Introduction to digital electronics,  Number Systems,  Logic gates,  Combinational logic circuits,  Basic Building Blocks,  Cascading of Building Blocks,  Design of Arithmetic circuits,  Design of logical functions using Basic building blocks,  Function implementation using ROM,  Assignments on Combinational logic circuits,  Lab session on Combinational logic circuits.

Module-IV :     ADVANCED DIGITAL DESIGN CONCEPTS-SEQUENTIAL

Sequential logic circuits,  Latches and Flip Flops,  Flip flops Conversion,  Shift Registers and Counters,  Synchronous and Asynchronous circuits,  Design and analysis,  Design and analysis of sequential circuits,  Random number generator,  Assignments on Sequential logic circuits.

Module-V :     RTL Coding Styles

Introduction to RTL coding,  Synthesizable and Non synthesizable constructs,  Synthesis coding styles,  Pipeline Modelling.

Module-VI :     BASIC STATIC TIMING ANALYSIS

Introduction to Static Timing Analysis,  Understanding Setup and Hold times,  Calculating the Critical Frequency.

Module-VII :     FINITE STATE MACHINE DESIGN

Designing a Sequence Detector,  State Assignment techniques,  Finite State Machine Coding Styles,  Designing a sequence detectors,  Mealy Style,  Moore Style,  Design and verification of a Sequence Detector,  Assignment on FSM's,  Lab Session on FSM's.

Module-VIII :     FPGA IMPLEMENTATION METHODOLOGY

Basic FPGA Architectures,  Configuring FPGA,  Clock Generation,  Lab Session: Assignments on FPGA.

Module-IX :     MINI PROJECT USING VERILOG HDL

Understand UART Specification,  Requirement Analysis,  Design Architecture preparation,  HAS ans MAS preparation,  HDL coding,  Functional Simulation,  Synthesis,  FPGA Device Program.

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