QSoCs Certified Design Verification Engineer (QCDVE)

Category

Full time

Duration

6 Months

Eligibility

BE/Btech or M.Sc in Electronics/Computer Science.

Timings

9am - 6pm weekdays, 10am - 1pm Saturday

Semiconductor industry is growing worldwide in a rapid pace, and creating jobs in large number. But the shortage of skilled and well trained resources is acting as a bottleneck for such a growth in India. Our certification course QCDVE is structured to fill the gap that exist between the fresh graduates from colleges and the industry in terms of technical and soft skill requirements. This training course includes soft skill development programs, industry expert's talk and projects on industry standard projects, in addition to the interactive classroom sessions from working professionals. Our course content reflects current industry trends.We share real-world, applied knowledge to help you expand and solidify your skills.

Key Features

  • Classes taken by working professionals from industry.
  • All Modules include hands on work.
  • Soft skill development programs.
  • Assignments with fully automated Verification flow.
  • 6 weeks project on Industry accepted protocols.
  • High end protocol implementation.
  • Low Power Design and Verification.
  • 100% placement assistance.

Modules

Module-1: BASIC DIGITAL DESIGN

Introduction to Digital system design, review of number systems and conversions, Boolean algebra, Switch level modeling of logic gates, universal gates, logic optimization techniques, Combinational building blocks.

Module-2: ADVANCED DIGITAL DESIGN

Analysis and Design of Combinational logic circuits, Design of combinational circuit design using tristate devices, Review of sequential elements: latches and flip-flops, Finite state machine design: Sequence detectors, frequency dividers, Frequency synthesizers, synchronous and asynchronous counter design, Shift Registers and Memory design, FPGA Architectures.
Design Project: Dice game from specifications.

Module-3: CMOS FUNDAMENTALS

Introduction to CMOS fundamentals, ideal and Non Ideal characteristics, BJT vs FET, CMOS inverter and its Characteristics, CMOS circuit design: NAND and NOR realizations, Transistor sizing, Layout and Stick Diagrams, CMOS Processing Steps, Fabrication, CMOS Technology - Current Trends.

Module-4: STATIC TIMING ANALYSIS

Static timing analysis: introduction to timing analysis, comparison of STA over DTA, need for STA, Introduction to clock domain, single and multi-clock domain, clock domain crossing, Static timing analysis concepts. Fixing timing issues.

Module -5: LINUX & SCRIPTING LANGUAGES

Introduction to LINUX operating systems, components of Linux systems, Directory structure, utilities and Commands, Vi Editors. Introduction to Perl, Functions and statements, Numbers and strings and quotes, comments and loops.

Module-6: VERILOG HDL BASICS

Introduction to Verilog HDL, Syntax and Semantics of Verilog HDL, Data types and operators, Introduction to Design methodologies, Styles of modeling: Data flow, Structural, Gate level and Behavioral. Verification using simple test bench.

Module-7: HDL PROGRAMMING

Continuous assignment statements, Procedural assignment statement, control flow statements, Blocking and Non-blocking, race condition, Tasks and functions, Finite state machine coding styles.

Module-8: RTL DESIGN

Synthesis: Introduction to synthesis, Registers in Verilog, Unwanted latches, operator synthesis, RTL coding styles.

Module-9: VERIFICATION USING VERILOG HDL

Introduction to verification, classification of verification, Compiler Directives, system tasks, File management, Verilog event scheduling, Advanced test bench styles: Self checking test bench, Memory based test bench, test bench using file management, randomized test bench.

Module-10: STANDARD PROJECT

RTL Design and RTL Verification: Introduction, Specification Analysis, Architecture Preparation, Architecture Review, RTL coding, Project Review.

Module-11: SYSTEM VERILOG HVL

Introduction to HVL’s,Data types, Arrays, Operators and expressions, Processes, Tasks and Functions, Loops and threads

Module-12:OOPS

Introduction, Properties and Methods, Static and Dynamic, Polymorphism, Inheritance

Module-13: RANDOMIZATION

Introduction, Random variables, Constraint Blocks, Methods for randomization, System functions for randomization

Module-14:INTER PROCESS COMMUNICATION

Introduction, Mailboxes, Semaphores, Events

Module-15: INTERFACE

Introduction, Modports, Virtual Interface, Clocking Blocks, need for clocking blocks

Module-16: PROGRAM BLOCK

Introduction, Advantage of Program Block, Coding guidelines, defining parameter

Module-17: COVERAGE AND ASSERTIONS

Introduction to Functional Coverage, cover group, Cover point and bins, Cross coverage, Predefined methods, Predefined system tasks and functions, Introduction to assertions, Immediate and concurrent assertions, Boolean expressions, sequences.

Module-18: TEST BENCH ARCHITECTURE

Introduction, Generator, Driver, Monitor, Scoreboard, Functional coverage

Module-19: PROJECT

Introduction, Specification Analysis, Architecture preparation, Architecture review, Coding, Project review

Module-20: INTRODUCTION TO UVM

Overview, UVM Architecture(overview), UVM factory, Components and Sequences, Sequencer, Driver, Monitor, Agent, Environment, Scoreboard, test, top module

Module-21: UVM BASICS

Tlm_ports, sequence item, sequence, uvm_macros, uvm_phases, running a simulation, uvm_reporting, resource db, configdb, Sequencer-driver communication

Module-22: UVM ADVANCED

Factory overriding, Virtual sequence, virtual sequencer

Module-23: PROJECT

Introduction, Specification Analysis, Architecture preparation, Architecture review, Coding, Project review

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