QSoCs Diploma in Design Verification (QDDV)

Category

Weekend Program

Duration

3 Months

Eligibility

BE/Btech or M.Sc in Electronics/Computer Science.

Timings

9am - 6pm weekdays, 10am - 1pm Saturday

Semiconductor industry is growing at high pace in India and causing huge demand for skilled professions. To address this demand QSoCs is launching new diploma program on Design and Verification. This is a 3 month duration program, focusing on Systemverilog, UVM and one industry standard project. This program is intended for the students who are very good in Digital concepts and electronics engineering basics. This training course includes soft skill development programs, industry expert's talk and projects on industry standard projects, in addition to the interactive classroom sessions from working professionals.

Key Features

  • Classes taken by working professionals from industry.
  • All Modules include hands on work.
  • Soft skill development programs.
  • Assignments with fully automated Verification flow.
  • 2 weeks project on Industry accepted protocols.

Modules

Module-1: DIGITAL DESIGN

Analysis and Design of Combinational logic circuits, Design of combinational circuit design using tristate devices, Review of sequential elements: latches and flip-flops, Finite state machine design: Sequence detectors, frequency dividers, Frequency synthesizers, synchronous and asynchronous counter design, Shift Registers and Memory design, FPGA Architectures.

Module -2: LINUX & SCRIPTING LANGUAGES

Introduction to LINUX operating systems, components of Linux systems, Directory structure, utilities and Commands, Vi Editors. Introduction to Perl, Functions and statements, Numbers and strings and quotes, comments and loops.

Module-3: VERILOG HDL BASICS

Introduction to Verilog HDL, Syntax and Semantics of Verilog HDL, Data types and operators, Introduction to Design methodologies, Styles of modeling: Data flow, Structural, Gate level and Behavioral. Verification using simple test bench.Continuous assignment statements, Procedural assignment statement, control flow statements, Blocking and Non-blocking, race condition, Tasks and functions, Finite state machine coding styles.

Module-4: VERIFICATION USING VERILOG HDL

Introduction to verification, classification of verification, Compiler Directives, system tasks, File management, Verilog event scheduling, Advanced test bench styles: Self checking test bench, Memory based test bench, test bench using file management, randomized test bench.

Module-5: SYSTEM VERILOG HVL

Introduction to HVL’s,Data types, Arrays, Operators and expressions, Processes, Tasks and Functions, Loops and threads

Module-6: OOPS & RANDOMIZATION

Introduction, Properties and Methods, Static and Dynamic, Polymorphism, Inheritance. Random variables, Constraint Blocks, Methods for randomization, System functions for randomization

Module-7: INTER PROCESS COMMUNICATION

Introduction, Mailboxes, Semaphores, Events

Module-8: INTERFACE

Introduction, Modports, Virtual Interface, Clocking Blocks, need for clocking blocks

Module-9: PROGRAM BLOCK

Introduction, Advantage of Program Block, Coding guidelines, defining parameter.

Module-10: COVERAGE AND ASSERTIONS

Introduction to Functional Coverage, cover group, Cover point and bins, Cross coverage, Predefined methods, Predefined system tasks and functions, Introduction to assertions, Immediate and concurrent assertions, Boolean expressions, sequences.

Module-11: TEST BENCH ARCHITECTURE

Introduction, Generator, Driver, Monitor, Scoreboard, Functional coverage

Module-12: PROJECT

Introduction, Specification Analysis, Architecture preparation, Architecture review, Coding, Project review

Module-13: INTRODUCTION TO UVM

Overview, UVM Architecture(overview), UVM factory, Components and Sequences, Sequencer, Driver, Monitor, Agent, Environment, Scoreboard, test, top module

Module-14: UVM BASICS

Tlm_ports, sequence item, sequence, uvm_macros, uvm_phases, running a simulation, uvm_reporting, resource db, configdb, Sequencer-driver communication

Module-15: UVM ADVANCED

Factory overriding, Virtual sequence, virtual sequencer

Module-16: PROJECT

Introduction, Specification Analysis, Architecture preparation, Architecture review, Coding, Project review

Enroll Here