Weekend SVUVM

Category

Weekend Program

Duration

9 Weekends

Eligibility

VLSI professionals/Interns

Timings

9.00am - 5pm on Saturday & 9.00am - 1pm on Sunday

This weekend program is aimed for working professional, who wants to improve their skills in the industry demanding HVL-Systemverilog and UVM. Functional verification of ICs is very much challenging nowadays because of the ever increasing demand for better performance with lower power and smaller dimension. This resulted in moving the verification environments from HDLs to HVLs, because of the additional features like oops, randomization, functional coverage etc that the later has. And slowly SystemVerilog with UVM methodology became the most commonly used verification approach by the semiconductor industry.

Key Features

  • Classes taken by working professionals from industry.
  • All Modules include hands on work.
  • Emphasized classed on oops concepts, randomization and functional coverage.
  • Assignments with fully automated Verification flow.
  • 2 weekends project on Industry accepted protocols.

Enroll Here