Workshop on RTL design and Verification

Category

Workshop Program

Duration

1 Day

Eligibility

B.Tech/B.E. from ECE, EEE, EE, IE- Freshers
ME/MTech/MS in Electronics/VLSI- Freshers

Timings

9:30 am - 04:00 pm

Session1: Theoretical Session

  • Introduction to Verilog
  • Design Methodologies
  • Design abstraction levels
  • Understanding ASIC and FPGA
  • System on Chip (SoC) design flow
  • Front End Design using Verilog Structural, Behavioral, RTL (Register Transfer Level)
  • RTL Design using Verilog
  • RTL verification using Verilog
  • Trainer - Design Lead with 12 years experience.

Session2: RTL Design LAB

Below VLSI Blocks discussed in detail and will be implemented:

  • FLIP FLOP / LATCHES
  • MUX
  • ADDERs , MULTIPLIERs
  • MEMORY
  • Sequence Detectors
  • Trainer - Verification Lead with 12 years experience.

Take Home Items:

  • Participation Certificate
Note: Registering here will not ensure your seat for the Free Internship. Selected candidates will get admission ticket over registered email.

Enroll Here